module sram (
    input sram_clk,
    
    input SRAM_CS_A_N,          //双端口，端口A，片选读写地址，写(进)读(出)信号
    input SRAM_WE_A_N,
    input [9:0]SRAM_ADDR_A,
    input [23:0]SRAM_WDATA_A,
    input SRAM_WDATA_OEA_N,
    output reg [23:0]SRAM_RDATA_A,
    
    
    input SRAM_CS_B_N,           //双端口，端口B
    input SRAM_WE_B_N,
    input [9:0]SRAM_ADDR_B,
    input [23:0]SRAM_WDATA_B,
    input SRAM_WDATA_OEB_N,
    output reg [23:0]SRAM_RDATA_B
);

reg[23:0] Mem[1023:0];

always@(posedge sram_clk)
    if(!SRAM_CS_A_N & !SRAM_WE_A_N & !SRAM_WDATA_OEA_N)
        Mem[SRAM_ADDR_A] <= SRAM_WDATA_A;
    else if(!SRAM_CS_B_N & !SRAM_WE_B_N & !SRAM_WDATA_OEB_N)
        Mem[SRAM_ADDR_B] <= SRAM_WDATA_B;

always@(posedge sram_clk)
    if(!SRAM_CS_A_N & SRAM_WE_A_N)
        SRAM_RDATA_A <= Mem[SRAM_ADDR_A];

//always@(posedge sram_clk)
//    if(!SRAM_CS_B_N & !SRAM_WE_B_N & !SRAM_WDATA_OEB_N)
//        Mem[SRAM_ADDR_B] <= SRAM_WDATA_B;

always@(posedge sram_clk)
    if(!SRAM_CS_B_N & SRAM_WE_B_N)
        SRAM_RDATA_B <= Mem[SRAM_ADDR_B];

//debug
wire cs_a_wren = !SRAM_CS_A_N & !SRAM_WE_A_N & !SRAM_WDATA_OEA_N;
wire cs_b_wren = !SRAM_CS_B_N & !SRAM_WE_B_N & !SRAM_WDATA_OEB_N;

wire[23:0]mem_data_0 = Mem[0];
wire[23:0]mem_data_1 = Mem[1];
wire[23:0]mem_data_2 = Mem[2];
wire[23:0]mem_data_3 = Mem[3];

endmodule
